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september 2015 docid028273 rev 1 1 / 14 this is information on a product in full production. www.st.com stl 120n4lf6ag automotive - grade n - channel 40 v, 3.0 m typ., 120 a stripfet? f6 power mosfet in a powerflat? 5x6 package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d p tot STL120N4LF6AG 40 v 3.6 m 120 a 96 w ? designed for automotive applications and aec - q101 qualified ? very low on - resistance ? very low gate charge ? high avalanche ruggedness ? low gate drive power loss ? wettabl e flanks package applications ? switching applications description this devic e is an n - channel power mosfet developed using the stripfet? f6 technology with a new trench gate structure. the resulting power mosfet exhibits very low r ds(on) in all packages. table 1: device summary order code marking package packing STL120N4LF6AG 120n4 l f6 powerflat? 5x6 tape and reel
contents STL120N4LF6AG 2 / 14 docid028273 rev 1 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteri stics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 8 4 package information ................................ ................................ ....... 9 4.1 powerflat? 5x6 wf type r package information .......................... 9 4.2 powerflat? 5x6 wf packing information ................................ .... 11 5 revision history ................................ ................................ ............ 13
STL120N4LF6AG electrical ratings docid028273 rev 1 3 / 14 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 40 v v ds drain - source voltage 20 v i d (1) drain current (continuous) at t c = 25 c 120 a i d (2) drain current (continuous) at t c = 25 c 55 a i d (2) drain current (continuous) at t c = 100 c 55 a i dm (3) drain current (pulsed) 220 a i d (4) drain current (continuous) at t pcb = 25 c 26 a i d (4) drain current (continuous) at t pcb = 100 c 19 a i dm (3) (4) drain current (pulsed) 104 a p tot total dissipation at t c = 25 c 96 w p tot (4) total dissipation at t pcb = 25 c 4.8 w t stg storage temperature - 55 to 175 c t j operating junction temperature notes: (1) this value is limited by the silicon (2) this value is limited by the package (3) pulse width is limited by safe operating area. (4) this value is rated according to r thj - pcb table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case 1.56 c/w r thj - pcb (1) thermal resistance junction - pcb 31.3 notes: (1) when mounted on 1 inch2 2 oz. cu board, t 10 s table 4: avalanche characteristics symbol parameter value unit i av avalanche current, repetitive or not repetitive (pulse width limited by maximum junction temperature) 26 a e as single pulse avalanche energy (t j = 25 c, i d = i av , v dd = 25 v) 200 mj
electrical characteristics STL120N4LF6AG 4 / 14 docid028273 rev 1 2 electrical characteristics (t c = 25 c unless otherwise specified) table 5: static symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 250 a 40 v i dss zero gate voltage drain current v gs = 0 v, v ds = 40 v 1 a v gs = 0 v, v ds = 40 v, tj = 125 c 10 a i gss gate - body leakage current v ds = 0 v, v gs = 20 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 1 3 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 13 a 3.0 3.6 m v gs = 5 v, i d = 13 a 3.2 4.5 table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 25 v, f = 1 mhz, v gs = 0 v - 4260 - pf c oss output capacitance - 647 - c rss reverse transfer capacitance - 373 - q g total gate charge v dd = 20 v, i d = 26 a, v gs = 10 v (see figure 14: "test circuit for gate charge behavior" ) - 80 - nc q gs gate - source charge - 1 5 - q gd gate - drain charge - 15 - r g intrinsic gate resistance f = 1 mhz, i d = 0 a - 1.5 - table 7: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 20 v, i d = 13 a r g = 4.7 , v gs = 10 v (see figure 13: "test circuit for resistive load switching times" and figure 18: "switching time waveform" ) - 20 - ns t r rise time - 70 - t d(off) turn - off - delay time - 40 - t f fall time - 20 -
STL120N4LF6AG electrical characteristics docid028273 rev 1 5 / 14 table 8: source drain diode symbol parameter test conditions min. typ. max. unit i sd (1) source - drain current - 26 a i sdm (2) source - drain current (pulsed) - 104 a v sd (3) forward on voltage v gs = 0 v, i sd = 13 a - 1.1 v t rr reverse recovery time i sd = 26 a, di/dt = 100 a/s, v dd = 25 v (see figure 15: "test circuit for inductive load switching and diode recovery times" ) - 40 ns q rr reverse recovery charge - 5.6 nc i rrm reverse recovery current - 2.8 a notes: (1) this value is rated according to r thj - pcb (2) pulse width is limited by safe operating area (3) pulse test: pulse duration = 300 s, duty cycle 1.5%
electrical characteristics STL120N4LF6AG 6 / 14 docid028273 rev 1 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance
STL120N4LF6AG electrical characteristics docid028273 rev 1 7 / 14 figure 8 : capacitance variations figure 9 : normalized gate threshold voltage vs temperature figure 10 : normalized on - resistance vs temperature figure 11 : normalized v(br)dss vs temperature figure 12 : source - drain diode forward characteristics
test circuits STL120N4LF6AG 8 / 14 docid028273 rev 1 3 test circuits figure 13 : test circuit for resistive load switching times figure 14 : test circuit for gate charge behavior figure 15 : test circuit for inductive load switching and diode recovery times figure 16 : unclamped inductive load test circuit figure 17 : unclamped inductive waveform figu re 18 : switching time waveform
STL120N4LF6AG package information docid028273 rev 1 9 / 14 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 powerflat? 5x6 wf type r package information figure 19 : powerflat? 5x6 wf type r package outline
package information STL120N4LF6AG 10 / 14 docid028273 rev 1 table 9: powerflat? 5x6 wf type r mechanical data dim. mm min. typ. max. a 0.80 1.00 a1 0.02 0.05 a2 0.25 b 0.30 0.50 d 5.00 5.20 5.40 e 6.20 6.40 6.60 d2 4.15 4. 45 e2 3.50 3.70 e 1.27 l 0.70 0.90 l1 0.275 k 1.275 1.575 e3 2.35 2.55 e4 0.40 0.60 e5 0.08 0.28 figure 20 : powerflat? 5x6 recommended footprint (dimensions are in mm)
STL120N4LF6AG package information docid028273 rev 1 11 / 14 4.2 powerflat? 5x6 wf packing information figure 21 : powerflat? 5x6 wf tape figure 22 : powerflat? 5x6 package orientation in carrier tape
package information STL120N4LF6AG 12 / 14 docid028273 rev 1 figure 23 : powerflat? 5x6 reel
STL120N4LF6AG revision history docid028273 rev 1 13 / 14 5 revision history table 10: document revision history date revision changes 25 - sep - 2015 1 first release.
STL120N4LF6AG 14 / 14 docid028273 rev 1 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics C all rights reserved

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